1. Field of the Invention
The present invention relates to a semiconductor device and manufacturing method thereof used for power control, and particularly to a planar-type insulated-gate field effect transistor and manufacturing method thereof.
2. Description of the Related Art
FIG. 25 is a sectional view showing a conventional planar-type insulated-gate field effect transistor (MOSFET). An Nxe2x88x92-epitaxial layer 2 is formed on an N+-silicon substrate 1 to make the drain region of the MOSFET. A plurality of P-base diffusion regions 3a and 3b are selectively formed by diffusion in the surface of the Nxe2x88x92-epitaxial layer 2. N+-source diffusion regions 4a and 4b are selectively formed by diffusion in the surfaces of the P-base diffusion regions 3a and 3b, respectively.
A gate electrode 6 of polycrystalline silicon is formed, through a gate oxide film 5, on the portion that extends from the N+-source diffusion region 4a and the P-base diffusion region 3a on one side, through a surface portion of the Nxe2x88x92-epitaxial layer 2, to the P-base diffusion region 3b and the N+-source diffusion region 4b on the other side. A source electrode 7 is formed on and connected to the P-base diffusion regions 3a and 3b and the N+-source diffusion regions 4a and 4b. A drain electrode 8 is formed on a surface of the N+-silicon substrate 1 opposite the Nxe2x88x92-epitaxial layer 2.
A MOSFET unit cell is formed of the N+-source diffusion region 4a and the Nxe2x88x92-epitaxial layer 2, with a channel region using a surface portion of the P-base diffusion region 3a under the gate electrode 6. When the gate electrode 6 is supplied with a positive voltage higher than a threshold value, an inversion layer appears in the surface of the channel region to bring the MOSFET into an ON-state. The ON-current flows from the drain electrode 8, through the N+-silicon substrate 1, Nxe2x88x92-epitaxial layer 2, the inversion layer formed in the channel region, and the N+-source diffusion region 4a, into the source electrode 7.
Since the MOSFET having this structure deals with a large current, the ON-resistance is preferably smaller. In an ON-state of the MOSFET, a current passageway is formed from the drain electrode 8 to the source electrode 7. Resistance components generated in the current passageway are roughly composed of a resistance (REpi) in the epitaxial portion of the Nxe2x88x92-epitaxial diffusion region 2, a resistance (RJFET) in the junction portion, and a channel resistance (Rch) in the channel region.
In order to reduce the ON-resistance, it is necessary to reduce the resistance (REpi) in the epitaxial portion. This is easily realized by increasing the impurity concentration of the Nxe2x88x92-epitaxial layer 2. However, where the impurity concentration of the Nxe2x88x92-epitaxial layer 2 is increased, the maximum value of electrical field intensity provided directly under the P-base diffusion regions 3a and 3b in an OFF-state of the MOSFET grows higher, thereby bringing about a decrease in the reverse breakdown voltage between the source and drain. Accordingly, it is necessary to control the impurity concentration of the Nxe2x88x92-epitaxial layer 2, so that the maximum value of an electrical field intensity to be obtained does not exceed the maximum value of the electrical field intensity of the Nxe2x88x92-epitaxial layer 2. As a result, the MOSFET shown in FIG. 25 is limited, in terms improvement to obtain both of a decreased ON-resistance and a stable reverse breakdown voltage between the source and drain.
Jpn. Pat. Appln. KOKAI Publication No. 9-191109 discloses a technique of forming P-buried layers in an Nxe2x88x92-epitaxial layer, in order to increase the impurity concentration of the Nxe2x88x92-epitaxial layer to reduce the ON-resistance, while to prevent the reverse breakdown voltage between the source and drain from lowering due to this. FIG. 26 is a sectional view showing a MOSFET structure of this kind with a high breakdown voltage MOSFET. An Nxe2x88x92-epitaxial layer 12 is formed on an N+-silicon substrate 11. A plurality of P-base diffusion regions 13a and 13b are selectively formed in the surface of the Nxe2x88x92-epitaxial layer 12. N+-source diffusion regions 14a and 14b are selectively formed in the surfaces of the P-base diffusion regions 13a and 13b, respectively.
A gate electrode 16 is formed, through a gate oxide film 15, on the portion that extends from the N+-source diffusion region 14a and the P-base diffusion region 13a on one side, through a surface portion of the Nxe2x88x92-epitaxial layer 12, to the P-base diffusion region 13b and the N+-source diffusion region 14b on the other side. A source electrode 17 is formed on and connected to the P-base diffusion regions 13a and 13b and the N+-source diffusion regions 14a and 14b. A drain electrode 8 is formed on a surface of the N+-silicon substrate 11. A plurality of P-buried layers 19a and 19b are formed in the Nxe2x88x92-epitaxial layer 12. The P-buried layers 19a and 19b are not connected to any portion, but are in an electrically floating state.
In this MOSFET with a high breakdown voltage, when a reversely applied voltage is low in an OFF-state, a depletion layer expands in the upper Nxe2x88x92-epitaxial layer 12 from the P-base diffusion regions 13a and 13b toward the drain electrode 18, as in the MOSFET shown in FIG. 25. At this time, the maximum electrical field intensity appears at a position near the interfaces between the P-base diffusion regions 13a and 13b and the Nxe2x88x92-epitaxial layer 12.
When the applied voltage reaches a certain value, a portion of the Nxe2x88x92-epitaxial layer 12 between the P-base diffusion regions 13a and 13b and the P-buried layers 19a are depleted, and the P-buried layers 19a are turned into a punch-through state, thereby fixing the electrical potential. Consequently, the maximum value of the electrical field on the P-base diffusion regions 13a and 13b side is prevented from increasing. When the applied voltage further increases, the depletion layer further expands in the Nxe2x88x92-epitaxial layer 12 toward the drain electrode 18. However, when the depletion layer reaches the P-buried layers 19b, the P-buried layers 19b are also turned into a punch-through state similarly to the punch-through state of the P-buried layers 19a, so that the maximum value of the electrical field is prevented from increasing.
However, even the semiconductor device shown in FIG. 26 entails the following problems. Specifically, since the P-buried layers 19a and 19b formed in the Nxe2x88x92-epitaxial layer are in an electrically floating state, their electrical potential fluctuates when the MOSFET is switched. Immediately after the device is changed from a reversely biased state into an ON-state, since holes in the P-buried layers 19a and 19b have disappeared, a high electrical potential is required for their depletion. So long as this electrical potential is held, a depletion layer expands in the Nxe2x88x92-epitaxial layer 12, and the resistance of the layer 12 increases. The holding time of the electrical potential in the P-buried layers 19a and 19b is too long to perform switching at high-speed.
Furthermore, when the P-buried layers 19a and 19b are formed, it is necessary to switch impurities for determining conductivity types so as to alternately grow the N -epitaxial layer 12 and the P-buried layers 19a and 19b. This operation complicates the manufacturing process, and may make the impurity concentration of the Nxe2x88x92-epitaxial layer 12 non-uniform. As a result, a stable reverse breakdown voltage can hardly be attained.
In light of the conventional problems described above, it is demanded to develop a semiconductor device and manufacturing method thereof, which reduce the ON-resistance of a MOSFET, while they improve the reverse breakdown voltage for a reverse bias applied between the source and drain.
According to a first aspect of the present invention, there is provided a semiconductor device comprising:
a semiconductor substrate of a first conductivity type;
a first semiconductor layer of the first conductivity type and a second semiconductor layer of a second conductivity type juxtaposed on the semiconductor substrate, the first semiconductor layer having an impurity concentration lower than that of the semiconductor substrate, the second semiconductor layer having at a central location a trench, which extends from an upper end of the second semiconductor layer toward the semiconductor substrate;
a first region of the second conductivity type formed to include an upper portion of the second semiconductor layer;
a second region of the first conductivity type formed in a surface of the first region; and
a gate electrode disposed, through an insulating film, on a channel region, which is a surface portion of the first region between the second region and an upper portion of the first semiconductor layer.
According to a second aspect of the present invention, there is provided a semiconductor device comprising:
a semiconductor substrate of a first conductivity type;
a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, and a third semiconductor layer of the first conductivity type juxtaposed on the semiconductor substrate, the first and third semiconductor layers having an impurity concentration lower than that of the semiconductor substrate, the third semiconductor layer having at a central location a trench, which extends from an upper end of the third semiconductor layer toward the semiconductor substrate;
a first region of the second conductivity type formed to include an upper portion of the second semiconductor layer;
a second region of the first conductivity type formed in a surface of the first region; and
a gate electrode disposed, through an insulating film, on a channel region, which is a surface portion of the first region between the second region and an upper portion of the third semiconductor layer.